Equilibrium Properties of a p-n Junction Diode

A p-n junction diode is formed when an opposite doping impurity (i.e., donor

or acceptor impurity) is introduced into a region of the semiconductor by using

the alloying, thermal diffusion, ion-implantation or epitaxial growth technique. For

example, a silicon p-n junction diode can be formed when a p-type doping impurity

such as boron (B), aluminum (Al), or gallium (Ga) is introduced into an n-type

silicon substrate via the thermal diffusion or ion-implantation process. On the other

hand, a silicon n-p junction diode is formed when an n-type doping impurity such as

phosphorus (P) or arsenic (As) impurity is introduced into a p-type silicon substrate.

The n-type doping impurity is called the donor impurity since it will contribute an

extra electron to the silicon lattice, while the p-type doping impurity is called the

acceptor impurity since it will give an extra hole to the silicon lattice. For the III-V

compound semiconductors such as GaAs, InP, InGaAs, and AlGaAs, a p-n junction

can be formed in these material systems by using different growth techniques such

as liquid-phase epitaxy (LPE), vapor-phase epitaxy (VPE), metal-organic chemical

vapor deposition (MOCVD), and molecular beam epitaxy (MBE).

Figure 11.1a and b shows the energy band diagrams of a p-n junction under

thermal equilibrium conditions before and after the intimate contacts. It should be

noted that the Fermi level is constant across the entire region of the p-n junction

under thermal equilibrium conditions. Figure 11.2a shows the charge distribution

in the p- and n-quasineutral regions as well as in the depletion region of the

junction. In general, depending on the doping impurity profile across the junction,

a diffused p-n junction may be approximated by either a step- (or abrupt-) junction

or a linear-graded junction. As shown in Figure 11.3a, the impurity profile for

a step junction changes abruptly across the metallurgical junction of the diode,

while the impurity profile for a linear-graded junction varies linearly with distance

across the junction, as is illustrated in Figure 11.3b.

The static properties of an abrupt p-n junction and a linear-graded p-n junction

diode are discussed next. The carrier distribution, built-in potential, electric field,

and potential profile in the junction space-charge region of a p-n junction diode

can be derived for both the abrupt- and linear-graded junctions using Poisson's

equation and continuity equations.

p-n Junction Diode Under Bias Conditions

When an external bias voltage is applied to a p-n junction diode, the thermal

equilibrium condition is disrupted and a current flow across the junction results.

Since the resistance across the depletion region is many orders of magnitude larger

than the resistance in the quasineutral regions, the voltage drops across both the

n- and p-quasineutral regions are negligible compared to the voltage drop across

the depletion region. Thus, it is reasonable to assume that the voltage applied to a

p-n junction diode is roughly equal to the voltage drop across the depletion layer

region. The current–voltage (I–V) characteristics of a p-n junction diode under

reverse- and forward-bias conditions are discussed next.

The current flow in a p-n junction depends on the polarity of the applied bias

voltage. Under forward-bias conditions, the current increases exponentially with

applied voltage. Under reverse-bias conditions, the current flow is limited mainly

by the thermal generation current and hence depends very little on the applied

voltage. Figure 11.4 shows the energy band diagrams for a p-n junction diode

under: (a) zero-bias, (b) forward-bias, and (c) reverse-bias conditions. As shown

in Figure 11.4b, when a forward-bias voltage V (i.e., positive polarity applied to

the p-side and negative to the n-side) is applied to the p-n junction, the potential

barrier across the junction will decrease to (Vbi − V). In this case, the potential

barrier for the majority carriers at the junction is reduced, and the depletion layer

width is decreased. Thus, under forward-bias condition a small increase in applied

voltage will result in a large increase in current flow across the junction. On the

other hand, if a reverse-bias voltage is applied to the junction, then the potential

barrier across the junction will increase to (Vbi + V), as shown in Figure 11.4c.

Therefore, under a reverse-bias condition the potential barrier for the majority

carriers and the depletion layer width will increase with increasing reverse-bias

voltage. As a result, current flow through the junction becomes very small, and the

junction impedance is extremely high.

The abrupt junction approximation is used to analyze the I–V characteristics of

a step-junction diode under bias conditions. In the analysis it is assumed that (1)

the entire applied voltage drop is only across the junction space-charge region,

and is negligible in the n- and p-quasineutral regions; (2) the solution of Poisson's

equation obtained under thermal equilibrium conditions can be modified to the

applied bias case, and (3) the total potential across the junction space-charge

region changes from Vbi for the equilibrium case to (Vbi ± V) when a bias voltage

is applied to the p-n junction


http://www.sli.ece.ufl.edu/eel6383/Chapter11.pdf

jose Leonardo Moncada Torres
c.i 18878408
EES

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